An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Bibtex

@inproceedings{f93ac542e36a4dacbb3f3bd91302eff2,
title = "An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI",
abstract = "An on-chip, low power, and area efficient charge-pump (CP) that generates a multiple of the supply voltage (VDD) in a single clock cycle is presented. The proposed CP utilizes parallel cross-connected CP units, which are implemented using MIM (metal-insulator-metal) capacitors. In the target application, i.e., a sub-threshold SRAM, the capacitors are accommodated on top of the memory banks to remove their area cost, which dominates in a CP realization. In this work, 66 instances of the proposed CP are fully integrated on-chip to assist read and write operations. The design is manufactured in a commercial 28nm FD-SOI technology and different design parameters were verified by measurements. The results verify an increased system-wise performance and power efficiency at a low area overhead of 3.7%. A performance of 37.5MHz for a boost ratio of 2×, and an average energy dissipation of 41 fJ per operation, was observed at 0.36V. ",
author = "Babak Mohammadi and Oskar Andersson and Xiao Luo and Masoud Nouripayam and Joachim Rodrigues",
year = "2017",
doi = "10.1109/ASSCC.2016.7844177",
language = "English",
pages = "229--232",
booktitle = "2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)",
publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",
note = "IEEE Asian Solid-State Circuits Conference (A-SSCC ). 2016 ; Conference date: 07-11-2016 Through 09-11-2016",

}