An ASIC Implementation for V-BLAST Detection in 0.35um CMOS

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

The V-BLAST system has been shown to be capable of exploiting the capacity advantage of multiple antenna systems. The square root algorithm for V-BLAST detection is attractive to hardware implementations due to low computational complexity and numerical stability. A low complexity VLSI architecture of the square root algorithm is presented in this paper. The proposed architecture is scalable for various configurations, and implemented in AMIS 0.35 /spl mu/m CMOS technology for a 4/spl times/4 QPSK V-BLAST system. When the received symbol packet length is larger than or equal to 100 bytes, the implemented chip can achieve a maximally possible detection throughput of 128/spl sim/160 Mb/s with a maximal clock frequency of 80 MHz.

Details

Authors
  • Zhan Guo
  • Peter Nilsson
Organisations
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Title of host publicationProceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004.
Pages95-98
Publication statusPublished - 2004
Publication categoryResearch
Peer-reviewedYes
EventFourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT - Rome, Italy
Duration: 2004 Dec 182004 Dec 21

Conference

ConferenceFourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT
CountryItaly
CityRome
Period2004/12/182004/12/21