An ASIC Implementation for V-BLAST Detection in 0.35um CMOS

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Standard

An ASIC Implementation for V-BLAST Detection in 0.35um CMOS. / Guo, Zhan; Nilsson, Peter.

Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004.. 2004. p. 95-98.

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Harvard

Guo, Z & Nilsson, P 2004, An ASIC Implementation for V-BLAST Detection in 0.35um CMOS. in Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004.. pp. 95-98, Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT, Rome, Italy, 2004/12/18. https://doi.org/10.1109/ISSPIT.2004.1433696

APA

Guo, Z., & Nilsson, P. (2004). An ASIC Implementation for V-BLAST Detection in 0.35um CMOS. In Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004. (pp. 95-98) https://doi.org/10.1109/ISSPIT.2004.1433696

CBE

Guo Z, Nilsson P. 2004. An ASIC Implementation for V-BLAST Detection in 0.35um CMOS. In Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004.. pp. 95-98. https://doi.org/10.1109/ISSPIT.2004.1433696

MLA

Guo, Zhan and Peter Nilsson "An ASIC Implementation for V-BLAST Detection in 0.35um CMOS". Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004.. 2004, 95-98. https://doi.org/10.1109/ISSPIT.2004.1433696

Vancouver

Guo Z, Nilsson P. An ASIC Implementation for V-BLAST Detection in 0.35um CMOS. In Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004.. 2004. p. 95-98 https://doi.org/10.1109/ISSPIT.2004.1433696

Author

Guo, Zhan ; Nilsson, Peter. / An ASIC Implementation for V-BLAST Detection in 0.35um CMOS. Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004.. 2004. pp. 95-98

RIS

TY - GEN

T1 - An ASIC Implementation for V-BLAST Detection in 0.35um CMOS

AU - Guo, Zhan

AU - Nilsson, Peter

PY - 2004

Y1 - 2004

N2 - The V-BLAST system has been shown to be capable of exploiting the capacity advantage of multiple antenna systems. The square root algorithm for V-BLAST detection is attractive to hardware implementations due to low computational complexity and numerical stability. A low complexity VLSI architecture of the square root algorithm is presented in this paper. The proposed architecture is scalable for various configurations, and implemented in AMIS 0.35 /spl mu/m CMOS technology for a 4/spl times/4 QPSK V-BLAST system. When the received symbol packet length is larger than or equal to 100 bytes, the implemented chip can achieve a maximally possible detection throughput of 128/spl sim/160 Mb/s with a maximal clock frequency of 80 MHz.

AB - The V-BLAST system has been shown to be capable of exploiting the capacity advantage of multiple antenna systems. The square root algorithm for V-BLAST detection is attractive to hardware implementations due to low computational complexity and numerical stability. A low complexity VLSI architecture of the square root algorithm is presented in this paper. The proposed architecture is scalable for various configurations, and implemented in AMIS 0.35 /spl mu/m CMOS technology for a 4/spl times/4 QPSK V-BLAST system. When the received symbol packet length is larger than or equal to 100 bytes, the implemented chip can achieve a maximally possible detection throughput of 128/spl sim/160 Mb/s with a maximal clock frequency of 80 MHz.

U2 - 10.1109/ISSPIT.2004.1433696

DO - 10.1109/ISSPIT.2004.1433696

M3 - Paper in conference proceeding

SN - 0-7803-8689-2

SP - 95

EP - 98

BT - Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004.

T2 - Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT

Y2 - 18 December 2004 through 21 December 2004

ER -