Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

We use a self-aligned, gate-last process providing n-type (InAs) and p-type (GaSb) MOSFET co-integration with a common gate-stack and demonstrate balanced drive current capability at about 100 μA/μm . By utilizing HSQ-spacers, control of gate-alignment allows to fabricate both n- and p-type devices based on the same type of vertical heterostructure InAs/GaSb nanowire with short gate-lengths down to 60 nm. Refined digital etch techniques, compatible with both sensitive antimonide structures and InAs, enable down to 16 nm diameter GaSb channel regions and 10 nm InAs channels. Balanced performance is showcased for both n- and p-type MOSFETs with Ion=156 μA/μm , at Ioff=100 nA/μm , and 98μA/μm , at |VDS|=0.5 , respectively.

Details

Authors
Organisations
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Other Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Logic gates, Nanoscale devices, MOSFET, Performance evaluation, Ions, Silicon, Metals
Original languageEnglish
Title of host publication2018 IEEE International Electron Devices Meeting (IEDM)
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages39.3.1-39.3.4
ISBN (Electronic)978-1-7281-1987-8
ISBN (Print)978-1-7281-1988-5
Publication statusPublished - 2019 Jan 17
Publication categoryResearch
Peer-reviewedYes
Event64th IEEE International Electron Devices Meeting - San Francisco, United States
Duration: 2018 Dec 12018 Dec 5
Conference number: 64

Conference

Conference64th IEEE International Electron Devices Meeting
Abbreviated titleIEDM 2018
CountryUnited States
CitySan Francisco
Period2018/12/012018/12/05

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