Capacitance Measurements in Vertical III-V Nanowire TFETs

Research output: Contribution to journalLetter

Abstract

By measuring scattering parameters over a wide range of bias points, we study the intrinsic gate capacitance as well as the charge partitioning of vertical nanowire tunnel field-effect transistors (TFETs). The gate-to-drain capacitance Cgd is found to largely dominate the on-state of TFETs, whereas the gate-to-source capacitance Cgs is sufficiently small to be completely dominated by parasitic components. This indicates that the tunnel junction on the source side almost completely decouples the channel charge from the small-signal variation in the source, while the absence of a tunnel junction on the drain side allows the channel charge to follow the drain small-signal variation much more directly.

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Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Other Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Vertical Nanowires, III-V, TFET, Small-signal model, Intrinsic Capacitance, RF, Cgd, Cgs
Original languageEnglish
Pages (from-to)943-946
Number of pages4
JournalIEEE Electron Device Letters
Volume39
Issue number7
Publication statusPublished - 2018 May 4
Publication categoryResearch
Peer-reviewedYes

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