Combining the parabolic synthesis methodology with second-degree interpolation

Research output: Contribution to journalArticle

Abstract

The Parabolic Synthesis methodology is an approximation methodology for implementing unary functions, such as trigonometric functions, logarithms and square root, as well as binary functions, such as division, in hardware. Unary functions are extensively used in baseband for wireless/wireline communication, computer graphics, digital signal processing, robotics, astrophysics, fluid physics, games and many other areas. For high-speed applications, as well as in low-power systems, software solutions are not sufficient and a hardware implementation is therefore needed. The Parabolic Synthesis methodology is a way to implement functions in hardware based on low complexity operations that are simple to implement in hardware. A difference in the Parabolic Synthesis methodology compared to many other approximation methodologies is that it is a multiplicative, in contrast to additive, methodology. To further improve the performance of Parabolic Synthesis based designs, the methodology is combined with Second-Degree Interpolation. The paper shows that the methodology provides a significant reduction in chip area, computation delay and power consumption with preserved characteristics of the error. To evaluate this, the logarithmic function was implemented, as an example, using the Parabolic Synthesis methodology in comparison to the Parabolic Synthesis methodology combined with Second-Degree Interpolation. To further demonstrate the feasibility of both methodologies, they have been compared with the CORDIC methodology. The comparison is made on the implementation of the fractional part of the logarithmic function with a 15-bit resolution. The designs implemented using the Parabolic Synthesis methodology - with and without the Second-Degree Interpolation - perform 4x and 8x better, respectively, than the CORDIC implementation in terms of throughput. In terms of energy consumption, the CORDIC implementation consumes 140% and 800% more energy, respectively. The chip area is also smaller in the case when the Parabolic Synthesis methodology combined with Second-Degree Interpolation is used.

Details

Authors
  • Erik Hertz
  • Bertil Svensson
  • Peter Nilsson
Organisations
External organisations
  • Halmstad University
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Signal Processing
  • Other Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Approximation, Arithmetic computation, CORDIC, Elementary functions, Look-up table, Parabolic synthesis, Second-degree interpolation, Unary functions, VLSI
Original languageEnglish
Pages (from-to)142-155
Number of pages14
JournalMicroprocessors and Microsystems
Volume42
Publication statusPublished - 2016 May 1
Publication categoryResearch
Peer-reviewedYes