Comparison of Low-Frequency Noise in Nanowire and Planar III-V MOSFETs

Research output: Contribution to conferencePaper, not in proceeding

Abstract

We compare III-V nanowire (NW) metal-oxidesemiconductor field-effect transistors (MOSFETs) in a vertical gate-all-around (GAA) as well as a lateral trigate architecture with planar reference MOSFETs and reveal that the NW geometry does not deteriorate the low-frequency noise (LFN) performance. In fact, with gate oxides deposited at the same conditions, the NW structures show potential to achieve better metrics due to slightly lower border trap densities Nbt. The normalized LFN in transistors with a higher number of NW can degrade due to averaging effects between individual nanowires within the same device.

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Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Other Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Low-Frequency Noise, MOSFETs, Nanowires (NWs)
Original languageEnglish
Publication statusPublished - 2019 Jul 2
Publication categoryResearch
Peer-reviewedNo
EventInsulating Films on Semiconductors (INFOS) - Cambridge, United Kingdom
Duration: 2019 Jun 302019 Jul 3
Conference number: 21

Conference

ConferenceInsulating Films on Semiconductors (INFOS)
Abbreviated titleINFOS
CountryUnited Kingdom
CityCambridge
Period2019/06/302019/07/03

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