Design and Measurement of a Variable-Rate Viterbi Decoder in 130-nm Digital CMOS

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This paper discusses design and measurements of a flexible Viterbi decoder
fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing
various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.


Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Pages (from-to)129-137
JournalMicroprocessors and Microsystems
Issue number2010
Publication statusPublished - 2010
Publication categoryResearch

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