Design of an area efficient crypto processor for 3GPP-LTE NB-IoT devices
Research output: Contribution to journal › Article
Providing information security is crucial for the Internet of Things (IoT) devices, platforms in which the available power budget is very limited. This paper tackles this challenge and presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) NarrowBand IoT (NB-IoT) standard. The proposed processor has been optimized to the needs of the low end portfolio technologies that compose the IoT market, which addresses low-area, low-cost and low-data rate applications. Operation analysis at the algorithm-level and hardware sharing at the architecture-level have enabled extensive area reduction. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a general purpose processor in a cycle accurate virtual platform. The design achieves a reduction of area ranging from 5% to 42% in comparison to similar work. Synthesis results using a 65-nm CMOS technology show that the processor has a hardware cost of 53.6 kGE, and is capable of performing at 52.4 Mbps for the block cipher and 800 Mbps for the stream cipher algorithms at a 100 MHz clock.
|Research areas and keywords||
Subject classification (UKÄ) – MANDATORY
|Journal||Microprocessors and Microsystems|
|Publication status||Published - 2020|