Efficient Hardware Implementations of Grain-128AEAD

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding


title = "Efficient Hardware Implementations of Grain-128AEAD",
abstract = "We implement the Grain-128AEAD stream cipher in hardware, using a 65 nm library. By exploring different optimization techniques, both at RTL level but also during synthesis, we first target high throughput, then low power. We reach over 33 GB/s targeting a high-speed design, at expense of power and area. We also show that, when targeting low power, the design only requires 0.23 $${\upmu }$$W running at 100 kHz. By unrolling the design, the energy consumed when encrypting a fixed length message decreases, making the 64 parallelized version the most energy efficient implementation, requiring only 11.2 nJ when encrypting a 64 kbit message. At the same time, the best throughput/power ratio is achieved at a parallelization of 4.",
keywords = "ASIC, Grain, Hardware design, NIST, Stream cipher",
author = "Jonathan S{\"o}nnerup and Martin Hell and Mattias S{\"o}nnerup and Ripudaman Khattar",
year = "2019",
doi = "10.1007/978-3-030-35423-7_25",
language = "English",
isbn = "9783030354220",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Gabler",
pages = "495--513",
editor = "Feng Hao and Sushmita Ruj and Sushmita Ruj and {Sen Gupta}, Sourav",
booktitle = "Progress in Cryptology – INDOCRYPT 2019 - 20th International Conference on Cryptology Proceedings",
address = "Germany",