Energy Efficient SQRD Processor for LTE-A using a Group-sort Update Scheme

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding


This paper presents an energy-efficient sorted QR decomposition (SQRD) processor for 3GPP LTE-Advanced (LTE-A) systems. The processor adopts a hybrid decomposition scheme to reduce computational complexity and provides a wide-range of performance complexity trade-offs. Based on the energy distribution of spatial channels, it switches between the brute-force SQRD and a low-complexity group-sort QR-update strategy, which is proposed in this work to effectively utilize the LTE-A pilot pattern. As a proof of concept, a run-time reconfigurable vector processor is developed to efficiently implement this adaptive-switching QR decomposition algorithm. In a 65nm CMOS technology, the proposed SQRD processor occupies 0.71 mm2 core area and has a throughput of up to 100MQRD/s. Compared to the brute-force approach, an energy reduction of 5~33% is achieved.


Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering


  • QR decomposition, Sorted QRD, LTE-A, MIMO, Energy
Original languageEnglish
Title of host publication[Host publication title missing]
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Print)978-1-4799-3431-7
Publication statusPublished - 2014
Publication categoryResearch
EventIEEE International Symposium on Circuits and Systems (ISCAS), 2014 - Melbourne, Austrailia, Melbourne, Australia
Duration: 2014 Jun 12014 Jun 5

Publication series

ISSN (Print)0271-4310
ISSN (Electronic)2158-1525


ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 2014

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