Energy-Efficient Redundant Execution for Chip Multiprocessors

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.

Details

Authors
External organisations
  • External Organization - Unknown
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Title of host publicationProceedings of the 20th symposium on Great lakes symposium on VLSI
Pages143-146
Publication statusPublished - 2010
Publication categoryResearch
Peer-reviewedYes
Externally publishedYes
EventGreat Lakes Symposium on VLSI (GLSVLSI'10) - Rhode Island, USA,
Duration: 2010 May 162010 May 18

Conference

ConferenceGreat Lakes Symposium on VLSI (GLSVLSI'10)
Period2010/05/162010/05/18