Energy-minimum sub-threshold self-timed circuits using current sensing completion detection

Research output: Contribution to journalArticle

Abstract

This study addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain and a generic implementation template using bundled-data circuitry and current sensing completion detection (CSCD). Furthermore, a fully decoupled latch controller was developed, which integrates with the current-sensing circuitry. Different configurations that utilise the proposed latch controller are highlighted. A contemporary synchronous electronic design automation tools-based design flow, which transforms a synchronous design into a corresponding self-timed circuit, is outlined. Different use cases of the CSCD system are examined. The design flow and the current-sensing technique are validated by the implementation of a self-timed version of a wavelet-based event detector for cardiac pacemaker applications in a standard 65 nm CMOS process. The chip was fabricated and verified to operate down to 250 mV. Spice simulations indicate a gain of 52.58% in throughput because of asynchronous operation. By trading the throughput improvement, energy dissipation is reduced by 16.8% at the energy-minimum supply voltage.

Details

Authors
Organisations
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • ASYNCHRONOUS CIRCUITS, CMOS INTEGRATED CIRCUITS, CMOS DIGITAL INTEGRATED CIRCUITS, VLSI
Original languageEnglish
Pages (from-to)342-353
JournalIET Computers and Digital Techniques
Volume5
Issue number4
Publication statusPublished - 2011
Publication categoryResearch
Peer-reviewedYes
Event16th IEEE International Symposium on Asynchronous Circuits and Systems - Grenoble, France
Duration: 2010 May 32010 May 6