III-V Nanowire MOSFET High-Frequency Technology Platform

Research output: ThesisDoctoral Thesis (compilation)


This thesis addresses the main challenges in using III-V nanowireMOSFETs for high-frequency applications by building a III-Vvertical nanowire MOSFET technology library. The initial devicelayout is designed, based on the assessment of the current III-V verticalnanowire MOSFET with state-of-the-art performance. The layout providesan option to scale device dimensions for the purpose of designing varioushigh-frequency circuits. The nanowire MOSFET device is described using1D transport theory, and modeled with a compact virtual source model.Device assessment is performed at high frequencies, where sidewall spaceroverlaps have been identified and mitigated in subsequent design iterations.In the final stage of the design, the device is simulated with fT > 500 GHz,and fmax > 700 GHz.Alongside the III-V vertical nanowire device technology platform, adedicated and adopted RF and mm-wave back-end-of-line (BEOL) hasbeen developed. Investigation into the transmission line parameters revealsa line attenuation of 0.5 dB/mm at 50 GHz, corresponding to state-ofthe-art values in many mm-wave integrated circuit technologies. Severalkey passive components have been characterized and modeled. The deviceinterface module - an interconnect via stack, is one of the prominentcomponents. Additionally, the approach is used to integrate ferroelectricMOS capacitors, in a unique setting where their ferroelectric behavior iscaptured at RF and mm-wave frequencies.Finally, circuits have been designed. A proof-of-concept circuit, designedand fabricated with III-V lateral nanowire MOSFETs and mm-wave BEOL, validates the accuracy of the BEOL models, and the circuit design. Thedevice scaling is shown to be reflected into circuit performance, in aunique device characterization through an amplifier noise-matched inputstage. Furthermore, vertical-nanowire-MOSFET-based circuits have beendesigned with passive feedback components that resonate with the devicegate-drain capacitance. The concept enables for device unilateralizationand gain boosting. The designed low-noise amplifiers have matching pointsindependent on the MOSFET gate length, based on capacitance balancebetween the intrinsic and extrinsic capacitance contributions, in a verticalgeometry. The proposed technology platform offers flexibility in device andcircuit design and provides novel III-V vertical nanowire MOSFET devicesand circuits as a viable option to future wireless communication systems.


Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering


  • MOSFET, III-V, nanowire (NW), Technology library, Process Monitor Structures, Radio Frequency, millimeter wave (mmWave), Compact Modelling, Circuit Design, Matching Networks, Low Noise Amplifier
Original languageEnglish
Supervisors/Assistant supervisor
Award date2021 May 28
  • Department of Electrical and Information Technology, Lund University
Print ISBNs978-91-7895-841-2
Electronic ISBNs978-91-7895-842-9
Publication statusPublished - 2021 May 4
Publication categoryResearch

Bibliographic note

Defence details Date: 2021-05-28 Time: 09:15 Place: Lecture hall E:1406, building E, Ole Römers väg 3, Faculty of Engineering LTH, Lund University, Lund. External reviewer(s) Name: Kallfass, Ingmar Title: Prof. Affiliation: University of Stuttgart, Germany. ---

Total downloads

No data available