Low power analog channel decoder in sub-threshold 65nm CMOS

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

This paper presents the architecture and the corresponding
simulation results for a very low power half-rate
extended Hamming (8,4) decoder implemented in analog integrated
circuitry. TI’s 65nm low power CMOS design library
was used to simulate the complete decoder including an input
interface, an analog decoding core and an output interface. The
simulated bit error rate (BER) performance of the decoder is
presented and compared to the ideal performance expected from
the Hamming code. Transistor-level simulation results suggest
that a high throughput Hamming decoder up to 1 Mbits can be
implemented in analog circuits with a core power consumption
as low as 6 μW.

Details

Authors
Organisations
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • sub-threshold CMOS, integrated circuits, low power circuits, Decoders
Original languageEnglish
Title of host publication[Host publication title missing]
PublisherSSoCC conference
Number of pages4
Publication statusPublished - 2010
Publication categoryResearch
Peer-reviewedNo
EventSwedish System-on-Chip Conference 2010 (SSoCC'10) - Kolmården, Sweden
Duration: 2010 May 32010 May 4

Conference

ConferenceSwedish System-on-Chip Conference 2010 (SSoCC'10)
CountrySweden
CityKolmården
Period2010/05/032010/05/04