Low-Frequency Noise in Nanowire and Planar III-V MOSFETs

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Nanowire geometries are leading contenders for future low-power transistor design. In this study, low-frequency noise is measured and evaluated in highly scaled III-V nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) and in planar III-V MOSFETs to investigate to what extent the device geometry affects the noise performance. Number fluctuations are identified as the dominant noise mechanism in both architectures. In order to perform a thorough comparison of the two architectures, a discussion of the underlying noise model is included. We find that the noise performance of the MOSFETs in a nanowire architecture is at least comparable to the planar devices. The input-referred voltage noise in the nanowire devices is superior by at least a factor of four.


Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Nano Technology


  • III-V, Nanowire (NW), MOSFET, Low-Frequency Noise, Gate Oxide Defects, Border Traps
Original languageEnglish
Article number110986
JournalMicroelectronic Engineering
Publication statusPublished - 2019 May 18
Publication categoryResearch

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