Realization of a floating-point A/D converter

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

A floating-point analog-to-digital converter (FP-ADC) with a linear architecture has been implemented using an amplifier network in front of a pipeline ADC. The amplifier network has outputs with binary weighted gains, each sampled separately. The signal with the proper gain is then converted in the ADC. This structure allows instant floating point exponent determination. The mismatches in the amplifier network has been analyzed and successfully reduced. A prototype FP-ADC is currently being manufactured in a 0.35 μm double-poly CMOS process. Post-layout simulations show an operating frequency in excess of 30 MS/s with 74 dB dynamic range and 8 bit resolution.

Details

Authors
  • Johan Piper
  • Jiren Yuan
Organisations
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Title of host publicationProceedings of 2001 IEEE International Symposium on Circuits and Systems
Pages404-407
Volume1
Publication statusPublished - 2001
Publication categoryResearch
Peer-reviewedYes
EventIEEE International Symposium on Circuits and Systems, ISCAS, 2001 - Sydney, NSW, Australia
Duration: 2001 May 62001 May 9

Publication series

Name
Volume1

Conference

ConferenceIEEE International Symposium on Circuits and Systems, ISCAS, 2001
CountryAustralia
CitySydney, NSW
Period2001/05/062001/05/09