A floating-point analog-to-digital converter (FP-ADC) with a linear architecture has been implemented using an amplifier network in front of a pipeline ADC. The amplifier network has outputs with binary weighted gains, each sampled separately. The signal with the proper gain is then converted in the ADC. This structure allows instant floating point exponent determination. The mismatches in the amplifier network has been analyzed and successfully reduced. A prototype FP-ADC is currently being manufactured in a 0.35 μm double-poly CMOS process. Post-layout simulations show an operating frequency in excess of 30 MS/s with 74 dB dynamic range and 8 bit resolution.
|Title of host publication||Proceedings of 2001 IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2001|
|Event||IEEE International Symposium on Circuits and Systems, ISCAS, 2001 - Sydney, NSW, Australia|
Duration: 2001 May 6 → 2001 May 9
|Conference||IEEE International Symposium on Circuits and Systems, ISCAS, 2001|
|Period||2001/05/06 → 2001/05/09|