Realization of a floating-point A/D converter

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Standard

Realization of a floating-point A/D converter. / Piper, Johan; Yuan, Jiren.

Proceedings of 2001 IEEE International Symposium on Circuits and Systems. Vol. 1 2001. p. 404-407.

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Harvard

Piper, J & Yuan, J 2001, Realization of a floating-point A/D converter. in Proceedings of 2001 IEEE International Symposium on Circuits and Systems. vol. 1, pp. 404-407, IEEE International Symposium on Circuits and Systems, ISCAS, 2001, Sydney, NSW, Australia, 2001/05/06. https://doi.org/10.1109/ISCAS.2001.921878

APA

Piper, J., & Yuan, J. (2001). Realization of a floating-point A/D converter. In Proceedings of 2001 IEEE International Symposium on Circuits and Systems (Vol. 1, pp. 404-407) https://doi.org/10.1109/ISCAS.2001.921878

CBE

Piper J, Yuan J. 2001. Realization of a floating-point A/D converter. In Proceedings of 2001 IEEE International Symposium on Circuits and Systems. pp. 404-407. https://doi.org/10.1109/ISCAS.2001.921878

MLA

Piper, Johan and Jiren Yuan "Realization of a floating-point A/D converter". Proceedings of 2001 IEEE International Symposium on Circuits and Systems. 2001, 404-407. https://doi.org/10.1109/ISCAS.2001.921878

Vancouver

Piper J, Yuan J. Realization of a floating-point A/D converter. In Proceedings of 2001 IEEE International Symposium on Circuits and Systems. Vol. 1. 2001. p. 404-407 https://doi.org/10.1109/ISCAS.2001.921878

Author

Piper, Johan ; Yuan, Jiren. / Realization of a floating-point A/D converter. Proceedings of 2001 IEEE International Symposium on Circuits and Systems. Vol. 1 2001. pp. 404-407

RIS

TY - GEN

T1 - Realization of a floating-point A/D converter

AU - Piper, Johan

AU - Yuan, Jiren

PY - 2001

Y1 - 2001

N2 - A floating-point analog-to-digital converter (FP-ADC) with a linear architecture has been implemented using an amplifier network in front of a pipeline ADC. The amplifier network has outputs with binary weighted gains, each sampled separately. The signal with the proper gain is then converted in the ADC. This structure allows instant floating point exponent determination. The mismatches in the amplifier network has been analyzed and successfully reduced. A prototype FP-ADC is currently being manufactured in a 0.35 μm double-poly CMOS process. Post-layout simulations show an operating frequency in excess of 30 MS/s with 74 dB dynamic range and 8 bit resolution.

AB - A floating-point analog-to-digital converter (FP-ADC) with a linear architecture has been implemented using an amplifier network in front of a pipeline ADC. The amplifier network has outputs with binary weighted gains, each sampled separately. The signal with the proper gain is then converted in the ADC. This structure allows instant floating point exponent determination. The mismatches in the amplifier network has been analyzed and successfully reduced. A prototype FP-ADC is currently being manufactured in a 0.35 μm double-poly CMOS process. Post-layout simulations show an operating frequency in excess of 30 MS/s with 74 dB dynamic range and 8 bit resolution.

U2 - 10.1109/ISCAS.2001.921878

DO - 10.1109/ISCAS.2001.921878

M3 - Paper in conference proceeding

SN - 0-7803-6685-9

VL - 1

SP - 404

EP - 407

BT - Proceedings of 2001 IEEE International Symposium on Circuits and Systems

T2 - IEEE International Symposium on Circuits and Systems, ISCAS, 2001

Y2 - 6 May 2001 through 9 May 2001

ER -