Reducing Leakage Power in Fixed Coefficient Arithmetic

Research output: Contribution to conferencePaper, not in proceeding

Abstract

Most of the power consumption has in the past been related to the dynamic activities, in a CMOS circuit. However, the static power, i.e. leakage, is a major contribution to the total power consumption, in present nano-meter scale technologies. This paper discusses static power reduction methodologies on architectural and arithmetical level. Novel arithmetic techniques to reduce the static power consumption in digital applications for nano-scale CMOS technologies are addressed. An arithmetic reduction of the static power consumption down to 5 % by using bit-serial arithmetic compared to bit-parallel is indicated.

Details

Authors
  • Peter Nilsson
Organisations
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Pages306-309
Publication statusPublished - 2007
Publication categoryResearch
Peer-reviewedYes
EventIEEE 14th International Conference on Electronics, Circuits and Systems (ICECS 2007) - Marrakech, Morocco
Duration: 2007 Dec 112007 Dec 14

Conference

ConferenceIEEE 14th International Conference on Electronics, Circuits and Systems (ICECS 2007)
CountryMorocco
CityMarrakech
Period2007/12/112007/12/14