Single input current-sensing differential logic (SCSDL)

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

A new novel single input current-sensing differential logic (SCSDL) is proposed. The SCSDL is flexible-in particular high input Boolean logic functions can be implemented with low complexity, area consumption, time delay, and power consumption. The first part of the area saving comes from the remarkable reduction of wiring; the other part comes from the very low number of transistors needed to implement a complex Boolean function, compared with other types of logic (e.g. CRDL, CSDL, DCVSL, static logic). Since this logic relies on comparison of currents in two branches, mismatch could ruin the function. The yield of the logic is good for a high performance process referred to mismatch.

Details

Authors
  • Roland Strandberg
  • Jiren Yuan
Organisations
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Title of host publicationProceedings of 2000 IEEE International Symposium on Circuits and Systems
Pages764-767
Volume1
Publication statusPublished - 2000
Publication categoryResearch
Peer-reviewedYes
EventIEEE International Symposium on Circuits and Systems (ISCAS), 2000 - Geneva, Switzerland
Duration: 2000 May 282000 May 31

Publication series

Name
Volume1

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 2000
Country/TerritorySwitzerland
CityGeneva
Period2000/05/282000/05/31