Template-assisted selective epitaxy of III-V nanoscale devices for co-planar heterogeneous integration with Si

Research output: Contribution to journalArticle

Abstract

III-V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III-V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 54002/V s, while the alongside fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at VDS = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneous material integration on Si.

Details

Authors
  • H. Schmid
  • Mattias Borg
  • K. Moselund
  • L. Gignac
  • C. M. Breslin
  • J. Bruley
  • D. Cutaia
  • H. Riel
External organisations
  • IBM Research Zurich
  • IBM Research
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Other Physics Topics
Original languageEnglish
Article number233101
JournalApplied Physics Letters
Volume106
Issue number23
Publication statusPublished - 2015 Jun 8
Publication categoryResearch
Peer-reviewedYes
Externally publishedYes