VLSI Implementation of a Soft-Output Signal Detector for Multi-Mode Adaptive MIMO Systems

Research output: Contribution to journalArticle


title = "VLSI Implementation of a Soft-Output Signal Detector for Multi-Mode Adaptive MIMO Systems",
abstract = "This paper presents a multimode soft-output multiple-input multiple-output (MIMO) signal detector that is efficient in hardware cost and energy consumption. The detector is capable of dealing with spatial-multiplexing (SM),break space-division-multiple-access (SDMA), and spatial-diversity (SD) signals of 4 ✕ 4 antenna and 64-QAM modulation. Implementation-friendly algorithms, which reuse most of the mathematical operations in these three MIMO modes, are proposed to provide accurate soft detection information, i.e., log-likelihood ratio, with much reduced complexity. A unified reconfigurable VLSI architecture has been developed to eliminate the implementation of multiple detector modules. In addition, several block level technologies, such as parallel metric update and fast bit-flipping, are adopted to enable a more efficient design. To evaluate the proposed techniques, we implemented the triple-mode MIMO detector in a 65-nm CMOS technology. The core area is 0.25 mm2 with 83.7 K gates. The maximum detecting throughput is 1 Gb/s at 167-MHz clock frequency and 1.2-V supply, which archives the data rate envisioned by the emerging long-term evolution advanced standard. Under frequency-selective channels, the detector consumes 59.3-, 10.5-, and 169.6-pJ energy per bit detection in SM, SD, and SDMA modes, respectively.",
author = "Liang Liu and Johan L{\"o}fgren and Peter Nilsson and Viktor {\"O}wall",
note = "There is a correction to the IEEE on-line version",
year = "2013",
doi = "10.1109/TVLSI.2012.2231706",
language = "English",
volume = "21",
pages = "2262--2273",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",
number = "12",