VLSI Implementation of a Soft-Output Signal Detector for Multi-Mode Adaptive MIMO Systems

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VLSI Implementation of a Soft-Output Signal Detector for Multi-Mode Adaptive MIMO Systems. / Liu, Liang; Löfgren, Johan; Nilsson, Peter; Öwall, Viktor.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 12, 2013, p. 2262-2273.

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TY - JOUR

T1 - VLSI Implementation of a Soft-Output Signal Detector for Multi-Mode Adaptive MIMO Systems

AU - Liu, Liang

AU - Löfgren, Johan

AU - Nilsson, Peter

AU - Öwall, Viktor

N1 - There is a correction to the IEEE on-line version

PY - 2013

Y1 - 2013

N2 - This paper presents a multimode soft-output multiple-input multiple-output (MIMO) signal detector that is efficient in hardware cost and energy consumption. The detector is capable of dealing with spatial-multiplexing (SM),break space-division-multiple-access (SDMA), and spatial-diversity (SD) signals of 4 ✕ 4 antenna and 64-QAM modulation. Implementation-friendly algorithms, which reuse most of the mathematical operations in these three MIMO modes, are proposed to provide accurate soft detection information, i.e., log-likelihood ratio, with much reduced complexity. A unified reconfigurable VLSI architecture has been developed to eliminate the implementation of multiple detector modules. In addition, several block level technologies, such as parallel metric update and fast bit-flipping, are adopted to enable a more efficient design. To evaluate the proposed techniques, we implemented the triple-mode MIMO detector in a 65-nm CMOS technology. The core area is 0.25 mm2 with 83.7 K gates. The maximum detecting throughput is 1 Gb/s at 167-MHz clock frequency and 1.2-V supply, which archives the data rate envisioned by the emerging long-term evolution advanced standard. Under frequency-selective channels, the detector consumes 59.3-, 10.5-, and 169.6-pJ energy per bit detection in SM, SD, and SDMA modes, respectively.

AB - This paper presents a multimode soft-output multiple-input multiple-output (MIMO) signal detector that is efficient in hardware cost and energy consumption. The detector is capable of dealing with spatial-multiplexing (SM),break space-division-multiple-access (SDMA), and spatial-diversity (SD) signals of 4 ✕ 4 antenna and 64-QAM modulation. Implementation-friendly algorithms, which reuse most of the mathematical operations in these three MIMO modes, are proposed to provide accurate soft detection information, i.e., log-likelihood ratio, with much reduced complexity. A unified reconfigurable VLSI architecture has been developed to eliminate the implementation of multiple detector modules. In addition, several block level technologies, such as parallel metric update and fast bit-flipping, are adopted to enable a more efficient design. To evaluate the proposed techniques, we implemented the triple-mode MIMO detector in a 65-nm CMOS technology. The core area is 0.25 mm2 with 83.7 K gates. The maximum detecting throughput is 1 Gb/s at 167-MHz clock frequency and 1.2-V supply, which archives the data rate envisioned by the emerging long-term evolution advanced standard. Under frequency-selective channels, the detector consumes 59.3-, 10.5-, and 169.6-pJ energy per bit detection in SM, SD, and SDMA modes, respectively.

U2 - 10.1109/TVLSI.2012.2231706

DO - 10.1109/TVLSI.2012.2231706

M3 - Article

VL - 21

SP - 2262

EP - 2273

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

T2 - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 12

ER -