Journal of Electronic Testing: Theory and Applications (JETTA), 0923-8174

Tidskrift

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  1. 2019
  2. Test Flow Selection for Stacked Integrated Circuits

    SenGupta, B., Nikolov, D., Dash, A. & Erik Larsson, 2019 aug 14, I : Journal of Electronic Testing: Theory and Applications (JETTA).

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  3. 2017
  4. Test Planning for Core-based Integrated Circuits under Power Constraints

    SenGupta, B., Nikolov, D., Ingelsson, U. & Erik Larsson, 2017 feb 1, I : Journal of Electronic Testing: Theory and Applications (JETTA). 33, 1, s. 7-23 17 s.

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  5. 2012
  6. Scheduling Tests for 3D Stacked Chips under Power Constraints

    Sengupta, B., Ingelsson, U. & Erik Larsson, 2012, I : Journal of Electronic Testing. 28, 1, s. 121-135

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  7. 2008
  8. A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling

    Erik Larsson & Peng, Z., 2008, I : Journal of Electronic Testing. 24, 5, s. 497-504

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  9. 2005
  10. Abort-on-Fail Based Test Scheduling

    Erik Larsson, Pouget, J. & Peng, Z., 2005, I : Journal of Electronic Testing. 21, 6, s. 651-658

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  11. Multiple Constraints Driven System-on-Chip Test Time Optimization

    Erik Larsson, Pouget, J. & Peng, Z., 2005, I : Journal of Electronic Testing. 21, 6, s. 599-611

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  12. 2002
  13. An Integrated Framework for the Design and Optimization of SOC Test Solutions

    Erik Larsson & Peng, Z., 2002, I : Journal of Electronic Testing. 18, 4-5, s. 385-400

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift