Pietro Andreani

Universitetslektor
Fler filtreringsmöjligheter
  1. 2020
  2. A 19.5-GHz 28-nm Class-C CMOS VCO, with a reasonably rigorous result on 1/f noise upconversion caused by short-channel effects

    Franceschin, A., Franceschin, A., Pietro Andreani, Padovan, F., Bassi, M. & Bevilacqua, A., 2020, I : IEEE Journal of Solid-State Circuits. 55, 7, s. 1842-1853 12 s., 9085341.

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  3. 2019
  4. A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS

    Siyu Tan, Sundstrom, L., Palm, M., Sven Mattisson & Pietro Andreani, 2019 nov 21, 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings. Nurmi, J., Ellervee, P., Halonen, K. & Roning, J. (red.). Institute of Electrical and Electronics Engineers Inc., 8906969

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  5. 2018
  6. An Accurate Analysis of Phase Noise in CMOS Ring Oscillators

    Pepe, F. & Pietro Andreani, 2018, I : IEEE Transactions on Circuits and Systems II: Express Briefs. s. 1-1

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  7. 2017
  8. A 2.8-3.8-GHz Low-Spur DTC-Based DPLL With a Class-D DCO in 65-nm CMOS

    Mahmoud, A., Pietro Andreani & Pepe, F., 2017 nov, I : IEEE Microwave and Wireless Components Letters. 27, 11, s. 1010-1012

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  9. On the Remarkable Performance of the Series-Resonance CMOS Oscillator

    Pepe, F., Bevilacqua, A. & Pietro Andreani, 2017 aug 1, I : IEEE Transactions on Circuits and Systems I: Regular Papers. 99, 12 s.

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  10. A general theory of phase noise in transconductor-based harmonic oscillators

    Pepe, F. & Pietro Andreani, 2017 feb 1, I : IEEE Transactions on Circuits and Systems I: Regular Papers. 64, 2, s. 432-445 14 s., 7723864.

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  11. 2016
  12. A continuous-time delta-sigma ADC with integrated digital background calibration

    Siyu Tan, Miao, Y., Palm, M., Joachim Neves Rodrigues & Pietro Andreani, 2016 nov 1, I : Analog Integrated Circuits and Signal Processing. 89, 2, s. 273-282 10 s.

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  13. A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications

    Mahmoud, A., Pietro Andreani & Lu, P., 2016 nov, I : Analog Integrated Circuits and Signal Processing. 89, 2, s. 337-345 9 s.

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  14. A 65 nm CMOS Wideband Radio Receiver with ΔΣ-Based A/D-Converting Channel-Select Filters

    Xiaodong Liu, Nejdel, A., Palm, M., Sundstrom, L., Markus Törmänen, Henrik Sjöland & Pietro Andreani, 2016 jul 1, I : IEEE Journal of Solid-State Circuits. 51, 7, s. 1566-1578 13 s., 7469322.

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  15. Still More on the 1/f2 Phase Noise Performance of Harmonic Oscillators

    Pepe, F. & Pietro Andreani, 2016 jun 1, I : IEEE Transactions on Circuits and Systems II: Express Briefs. 63, 6, s. 538-542 5 s., 7407326.

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  16. A 2.8-to-5.8 GHz harmonic VCO based on an 8-shaped inductor in a 28 nm UTBB FD-SOI CMOS process

    Mahmoud, A., Fanori, L., Mattsson, T., Caputa, P. & Piero Andreani, 2016 maj 23, I : Analog Integrated Circuits and Signal Processing. 88, 3, s. 391-399 9 s.

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  17. A 2.2ps 2-D Gated-Vernier Time-to-Digital Converter with Digital Calibration

    Lu, P., Wu, Y. & Piero Andreani, 2016 mar 29, I : IEEE Transactions on Circuits and Systems II: Express Briefs. s. 1019 - 1023 5 s.

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  18. 2015
  19. A 0.6-3.0 GHz 65 nm CMOS Radio Receiver with DS-based A/D-Converting Channel-Select Filters

    Nejdel, A., Xiaodong Liu, Palm, M., Sundström, L., Markus Törmänen, Henrik Sjöland & Pietro Andreani, 2015, [Host publication title missing]. IEEE - Institute of Electrical and Electronics Engineers Inc., 4 s.

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  20. A 2.8-to-5.8 GHz harmonic VCO in a 28 nm UTBB FD-SOI CMOS process

    Fanori, L., Mahmoud, A., Mattsson, T., Caputa, P., Rämö, S. & Piero Andreani, 2015, 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE - Institute of Electrical and Electronics Engineers Inc., s. 195 - 198

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  21. A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise

    Mahmoud, A., Piero Andreani & Lu, P., 2015, Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC).

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  22. A low-power 2nd-order CT delta-sigma modulator with an asynchronous SAR quantizer

    Radjen, D., Anderson, M., Sundstrom, L. & Pietro Andreani, 2015, I : Analog Integrated Circuits and Signal Processing. 84, 3, s. 409-420

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  23. Digital background calibration in continuous-time delta-sigma analog to digital converters

    Siyu Tan, Miao, Y., Andersson, M., Joachim Rodrigues & Piero Andreani, 2015, Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015 . IEEE - Institute of Electrical and Electronics Engineers Inc.

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  24. 2014
  25. A 1-1 MASH 2-D Vernier Time-to-Digital Converter with 2nd-order noise shaping

    Lu, P. & Pietro Andreani, 2014, [Host publication title missing]. IEEE - Institute of Electrical and Electronics Engineers Inc., s. 1324-1327 4 s.

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  26. A 2.4-to-5.3GHz Dual-Core CMOS VCO with Concentric 8-Shaped Coils

    Fanori, L., Mattsson, T. & Pietro Andreani, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). IEEE - Institute of Electrical and Electronics Engineers Inc., Vol. 57. s. 370

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  27. A Class-D CMOS DCO with an on-chip LDO

    Fanori, L., Mattsson, T. & Pietro Andreani, 2014, Proceedings Of The 40th European Solid-State Circuit Conference (ESSCIRC 2014). IEEE - Institute of Electrical and Electronics Engineers Inc., s. 335-338

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  28. A Filtering Delta Sigma ADC for LTE and Beyond

    Andersson, M., Andersson, M., Sundström, L., Mattisson, S. & Pietro Andreani, 2014, I : IEEE Journal of Solid-State Circuits. 49, 7, s. 1535-1547

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  29. A low-power 2nd-order CT delta-sigma modulator with a single operational amplifier

    Radjen, D., Anderson, M., Sundstrom, L. & Pietro Andreani, 2014, I : Analog Integrated Circuits and Signal Processing. 80, 3, s. 387-397

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  30. An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS

    Xiaodong Liu, Andersson, M., Anderson, M., Sundstrom, L. & Pietro Andreani, 2014, 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). IEEE - Institute of Electrical and Electronics Engineers Inc., s. 2337-2340

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  31. A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers

    Liscidini, A., Fanori, L., Pietro Andreani & Castello, R., 2014, I : IEEE Journal of Solid-State Circuits. 49, 3, s. 646-656

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  32. 2013
  33. A 2.7-6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2

    Bevilacqua, A. & Pietro Andreani, 2013, I : Analog Integrated Circuits and Signal Processing. 74, 1, s. 11-20

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  34. A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency

    Lu, P., Pietro Andreani & Liscidini, A., 2013, I : Analog Integrated Circuits and Signal Processing. 76, 2, s. 195-206

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  35. A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency

    Lu, P., Pietro Andreani & Liscidini, A., 2013, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2013. IEEE - Institute of Electrical and Electronics Engineers Inc., s. 151-154

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  36. A 9MHz Filtering ADC with Additional 2nd-Order Delta-Sigma Modulator Noise Suppression

    Andersson, M., Andersson, M., Sundström, L. & Pietro Andreani, 2013, Proceedings of the ESSCIRC (ESSCIRC), 2013. IEEE - Institute of Electrical and Electronics Engineers Inc., s. 323-326

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  37. A Push-Pull Class-C CMOS VCO

    Mazzanti, A. & Pietro Andreani, 2013, I : IEEE Journal of Solid-State Circuits. 48, 3, s. 724-732

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  38. A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing

    Ye, D., Lu, P., Pietro Andreani & Zee, R. V. D., 2013, [Host publication title missing]. ISCAS, s. 169-172

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  39. Class-D CMOS Oscillators

    Fanori, L. & Pietro Andreani, 2013, I : IEEE Journal of Solid-State Circuits. 48, 12, s. 3105-3119

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  40. Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs

    Fanori, L. & Pietro Andreani, 2013, I : IEEE Journal of Solid-State Circuits. 48, 7, s. 1730-1740

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  41. Theory and Design of a CT Delta Sigma Modulator with Low Sensitivity to Loop-Delay Variations

    Andersson, M., Sundström, L., Andersson, M. & Pietro Andreani, 2013, I : Analog Integrated Circuits and Signal Processing. 76, 3, s. 353-366

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  42. 2012
  43. A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS

    Abdulaziz, M., Shakir, M., Lu, P. & Pietro Andreani, 2012.

    Forskningsoutput: KonferensbidragKonferensabstract

  44. A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps

    Lu, P., Liscidini, A. & Pietro Andreani, 2012, I : IEEE Journal of Solid-State Circuits. 47, 7, s. 1626-1635

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  45. A 7.5 mW 9 MHz CT Delta-Sigma Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations

    Andersson, M., Andersson, M., Sundström, L. & Pietro Andreani, 2012, IEEE Asian Solid State Circuits Conference (A-SSCC), 2012. IEEE - Institute of Electrical and Electronics Engineers Inc., s. 245-248

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  46. A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter

    Lu, P., Wu, Y. & Pietro Andreani, 2012, [Host publication title missing]. IEEE - Institute of Electrical and Electronics Engineers Inc., s. 2593-2596 4 s.

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  47. A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter

    Lu, P., Liscidini, A. & Pietro Andreani, 2012, (Accepted/In press). 4 s.

    Forskningsoutput: KonferensbidragKonferenspaper, ej i proceeding/ej förlagsutgivet

  48. A Continuous Time Delta-Sigma Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback

    Radjen, D., Andersson, M., Sundström, L. & Pietro Andreani, 2012, I : Analog Integrated Circuits and Signal Processing.

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  49. An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators

    Bevilacqua, A. & Pietro Andreani, 2012, I : IEEE Transactions on Circuits and Systems Part 1: Regular Papers. 59, 5, s. 938-945

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  50. Harmonic Rejection Mixer at ADC Input for Complex IF Dual Carrier Receiver Architecture

    Sundström, L., Andersson, M., Andersson, M. & Pietro Andreani, 2012, Radio Frequency Integrated Circuits Symposium (RFIC), 2012. IEEE - Institute of Electrical and Electronics Engineers Inc., s. 265-268

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  51. Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference

    Corsi, M., Pietro Andreani, Ki, W-H., Chien, G. & Kenney, J., 2012, I : IEEE Journal of Solid-State Circuits. 47, 12, s. 2859-2864

    Forskningsoutput: TidskriftsbidragDebate/Note/Editorial

  52. Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator

    Bevilacqua, A. & Pietro Andreani, 2012, I : IEEE Transactions on Circuits and Systems II: Express Briefs. 59, 1, s. 20-24

    Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

  53. 2011
  54. A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS

    Abdulaziz, M., Shakir, M., Lu, P. & Pietro Andreani, 2011, [Host publication title missing]. 4 s.

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  55. A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution

    Lu, P., Pietro Andreani & Liscidini, A., 2011, [Host publication title missing]. s. 459-462

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  56. A 9-band WCDMA/EDGE transceiver supporting HSPA evolution

    Nilsson, M., Mattisson, S., Klemmer, N., Andersson, M., Arnborg, T., Caputa, P., Ek, S., Fan, L., Fredriksson, H., Garrigues, F., Geis, H., Hagberg, H., Hedestig, J., Huang, H., Kagan, Y., Karlsson, N., Kinzel, H., Mattsson, T., Mills, T., Mu, F. & 21 andra, Mårtensson, A., Nicklasson, L., Oredsson, F., Ozdemir, U., Park, F., Pettersson, T., Påhlsson, T., Pålsson, M., Ramon, S., Sandgren, M., Sandrup, P., Stenman, A-K., Strandberg, R., Sundström, L., Tillman, F., Tired, T., Uppathil, S., Walukas, J., Westesson, E., Zhang, X. & Pietro Andreani, 2011, [Host publication title missing]. s. 366-368

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  57. A continuous time delta sigma modulator with reduced clock jitter through DSCR feedback

    Radjen, D., Andersson, M., Sundström, L. & Pietro Andreani, 2011.

    Forskningsoutput: KonferensbidragKonferenspaper, ej i proceeding/ej förlagsutgivet

  58. A Digital PLL with a Multi-Delay Coarse-Fine TDC

    Wu, Y., Lu, P. & Pietro Andreani, 2011, [Host publication title missing]. 4 s.

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

  59. A mixed mode design flow for multi GHz ADPLLs

    Shakir, M., Abdulaziz, M., Lu, P. & Pietro Andreani, 2011, [Host publication title missing]. IEEE - Institute of Electrical and Electronics Engineers Inc., 4 s.

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

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