1/f Noise Sources in Dual-Gated Indium Arsenide Nanowire Transistors

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1/f Noise Sources in Dual-Gated Indium Arsenide Nanowire Transistors. / Delker, Collin J.; Kim, Seongmin; Borg, Mattias; Wernersson, Lars-Erik; Janes, David B.

I: IEEE Transactions on Electron Devices, Vol. 59, Nr. 7, 2012, s. 1980-1987.

Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

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Delker, Collin J. ; Kim, Seongmin ; Borg, Mattias ; Wernersson, Lars-Erik ; Janes, David B. / 1/f Noise Sources in Dual-Gated Indium Arsenide Nanowire Transistors. I: IEEE Transactions on Electron Devices. 2012 ; Vol. 59, Nr. 7. s. 1980-1987.

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TY - JOUR

T1 - 1/f Noise Sources in Dual-Gated Indium Arsenide Nanowire Transistors

AU - Delker, Collin J.

AU - Kim, Seongmin

AU - Borg, Mattias

AU - Wernersson, Lars-Erik

AU - Janes, David B.

PY - 2012

Y1 - 2012

N2 - 1/f noise is studied in dual-gated InAs nanowire transistors consisting of an omega top gate with high-k atomic layer deposited dielectric and silicon dioxide to substrate back gate. Noise spectra at varying gate bias combinations are compared from devices with differing top-gate lengths to separate the noise contributions of the top-gated channel from the ungated access portion, including the metal-nanowire contacts. For a given device geometry, it is possible to bias the device into four different regimes where the resistance and the noise amplitude can each be independently dominated by either the channel or the access/contact regions. When the device is fully in the on state, the access/contact regions dominate both resistance and noise. When the device is operating near or below threshold, the channel dominates resistance and noise. For the lowest amount of overall 1/f noise, most of the nanowire should be covered by the top gate, minimizing the access region length.

AB - 1/f noise is studied in dual-gated InAs nanowire transistors consisting of an omega top gate with high-k atomic layer deposited dielectric and silicon dioxide to substrate back gate. Noise spectra at varying gate bias combinations are compared from devices with differing top-gate lengths to separate the noise contributions of the top-gated channel from the ungated access portion, including the metal-nanowire contacts. For a given device geometry, it is possible to bias the device into four different regimes where the resistance and the noise amplitude can each be independently dominated by either the channel or the access/contact regions. When the device is fully in the on state, the access/contact regions dominate both resistance and noise. When the device is operating near or below threshold, the channel dominates resistance and noise. For the lowest amount of overall 1/f noise, most of the nanowire should be covered by the top gate, minimizing the access region length.

KW - Indium Arsenide

KW - low-frequency noise

KW - nanowire FETs

U2 - 10.1109/TED.2012.2194150

DO - 10.1109/TED.2012.2194150

M3 - Article

VL - 59

SP - 1980

EP - 1987

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 7

ER -