A low latency and area efficient FFT processor for massive MIMO systems

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

Abstract

A low-latency and area-efficient FFT/IFFT scheme is presented. The main idea is to utilize OFDM guard bands to reduce the operation counts and processing time, which results in 42% latency reduction compared to the reported pipelined schemes. To realize this idea, a modified pipelined architecture and an efficient data scheduling scheme are proposed. Furthermore, the proposed architecture is scalable to different FFT sizes and is also reconfigurable to support a wide range of applications. A 2048-point FFT/IFFT processor based on the proposed scheme has been designed, resulting in 1200 clock cycles latency, which can address the low latency demand of massive MIMO systems. Synthesis results in a 28 nm CMOS technology show that proposed design attains a throughput of 1 GS/s when clocked at 500 MHz.

Detaljer

Författare
Enheter & grupper
Forskningsområden

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Annan elektroteknik och elektronik
  • Kommunikationssystem

Nyckelord

Originalspråkengelska
Titel på värdpublikationIEEE International Symposium on Circuits and Systems (ISCAS), 2017 - Proceedings
FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor1-4
Antal sidor4
ISBN (elektroniskt)978-1-4673-6853-7
ISBN (tryckt)978-1-5090-1427-9
StatusPublished - 2017 sep 28
PublikationskategoriForskning
Peer review utfördJa
Evenemang50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, USA
Varaktighet: 2017 maj 282017 maj 31

Konferens

Konferens50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
LandUSA
OrtBaltimore
Period2017/05/282017/05/31