A non-feedback multiphase clock generator

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

Abstract

This paper introduces the design of a new multiphase clock generator with no feedback loop. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1.5 GHz

Detaljer

Författare
  • Yang Lixin
  • Zhou Yijun
  • Jiren Yuan
Enheter & grupper
Forskningsområden

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Elektroteknik och elektronik

Nyckelord

Originalspråkengelska
Titel på värdpublikation2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)
FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor389-392
ISBN (tryckt)0-7803-7448-7
StatusPublished - 2002
PublikationskategoriForskning
Peer review utfördJa
Evenemang2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ
Varaktighet: 2002 maj 262002 maj 29

Konferens

Konferens2002 IEEE International Symposium on Circuits and Systems
Period2002/05/262002/05/29