A PLL based 12GHz LO generator with digital phase control in 90nm CMOS

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

Abstract

A 12 GHz PLL with digital output phase control
has been implemented in a 90 nm CMOS process. It is intended
for LO signal generation in integrated phased array transceivers.
Locally placed PLLs eliminate the need of long high frequency
LO routing to each transceiver in a phased array circuit.
Routing losses are thereby reduced and design of integrated
phased array transceivers become more modular. A chip was
manufactured, featuring two separate fully integrated PLLs
operating at 12 GHz, with a common 1.5 GHz reference. The chip,
including pads, measures 1050x700 μm2. Each PLL consumes
15 mA from a 1.2 V supply, with a typical measured phase noise
of -110 dBc/Hz at 1 MHz offset. The phase control range exceeds
360.

Detaljer

Författare
Enheter & grupper
Forskningsområden

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Elektroteknik och elektronik

Nyckelord

Originalspråkengelska
Titel på värdpublikationProc. 2009 IEEE Asia Pacific Microwave Conference, APMC 2009, Singapore
Sidor289-292
StatusPublished - 2009
PublikationskategoriForskning
Peer review utfördJa
EvenemangAsia Pacific Microwave Conference, APMC 2009 - Singapore, Singapore
Varaktighet: 2009 dec 7 → …

Konferens

KonferensAsia Pacific Microwave Conference, APMC 2009
LandSingapore
Period2009/12/07 → …