A Self-aligned Gate-last Process applied to All-III-V CMOS on Si
Forskningsoutput: Tidskriftsbidrag › Artikel i vetenskaplig tidskrift
Abstract
Vertical nanowire n-type (InAs) and p-type (GaSb) transistors are
co-processed and co-integrated using a gate-last process, enabling short
gate-lengths (Lg=40 nm) and allowing selective digital etching of the
channel. Two different common gate-stacks, including various
pre-treatments, were compared and evaluated. The process was optimized
to achieve high n-type performance while demonstrating p-type operation.
The best n-type device is scaled down to 12 nm diameter and has a peak
transconductance of 2.6 mS/μm combined with a low Ron of 317 Ω·μm while
the p-type exhibit 74 μS/μm. In spite of increased complexity due to
co-integration, our n-type InAs transistors demonstrate increased
drive-current, 1.8 mA/μm, compared to earlier publications.
Detaljer
Författare | |
---|---|
Enheter & grupper | |
Forskningsområden | Ämnesklassifikation (UKÄ) – OBLIGATORISK
Nyckelord |
Originalspråk | engelska |
---|---|
Sidor (från-till) | 935-938 |
Tidskrift | IEEE Electron Device Letters |
Volym | 39 |
Utgåva nummer | 7 |
Tidigt onlinedatum | 2018 maj 16 |
Status | Published - 2018 jul |
Publikationskategori | Forskning |
Peer review utförd | Ja |
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