An Adaptive QR Decomposition Processor for Carrier Aggregated LTE-A in 28 nm FD-SOI

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This paper presents an adaptive QR decomposition (QRD) processor for five-band carrier aggregated LTE-A
downlinks. The design uses time and frequency correlation
properties of wireless channels to reduce QRD computations
while maintaining an uncoded bit error rate loss below 1 dB.
An analysis on the performance of a linear interpolating QRD is
presented and optimum distances for different channel conditions
are suggested. The Householder transform suited for spatially
correlated scenarios is chosen and modified for concurrent vector
rotations resulting in high throughput. Based on these, a parallel
hardware architecture suitable for easy reconfigurability and low power is developed and fabricated in 28 nm FD-SOI technology. The QRD unit occupies 205 k gates of logic and has a maximum throughput of 22 M QRD/s while consuming 29 mW of power. On a circuit level, the back gate feature is leveraged to double operational frequency in low time-frequency correlation channels or to lower power consumption to 1.9 mW in favorable conditions. The proposed system provides designers with multiple levels of adaptive control from architectural to circuit level for power-performance trade-offs and is well suited for mobile devices operating on limited battery energy.


Enheter & grupper

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Elektroteknik och elektronik


TidskriftIEEE Transactions on Circuits and Systems I: Regular Papers
Tidigt onlinedatum2017
StatusPublished - 2017
Peer review utfördJa