An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error average

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

Abstract

A multiphase clock generator based on direct phase interpolation is presented. No feedback loop is required. A simple phase interpolation architecture is proposed, in which the two phase-adjacent signals are interpolated by using a series of resistors via inverters' discharging or charging slopes to generate multiphase outputs in a single stage. A phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The measured performance shows it can operate at the input clock frequencies from 300 MHz to 600 MHz and has the rms jitter of 6 ps at 500 MHz.

Detaljer

Författare
  • Yang Lixin
  • Jiren Yuan
Enheter & grupper
Forskningsområden

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Elektroteknik och elektronik

Nyckelord

Originalspråkengelska
Titel på värdpublikationProceedings - IEEE International Symposium on Circuits and Systems
FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor645-648
Volym1
StatusPublished - 2003
PublikationskategoriForskning
Peer review utfördJa
EvenemangProceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
Varaktighet: 2003 maj 252003 maj 28

Publikationsserier

Namn
Volym1
ISSN (tryckt)0271-4310
ISSN (elektroniskt)2158-1525

Konferens

KonferensProceedings of the 2003 IEEE International Symposium on Circuits and Systems
LandThailand
OrtBangkok
Period2003/05/252003/05/28