An Architecture for Combined Test Data Compression and Abort-on-Fail Test

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

Abstract

The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and long test application times. In contrast to previous approaches that address either test data compression or abort-on-fail testing, we propose an architecture for combined test data compression and abort-on-fail testing. The architecture improves throughput through multi-site testing as the ATE memory requirement is constant and independent of the degree of multi-site testing. For flexibility in modifying the test data at any time, we make use of a test program for decompression; only test independent evaluation logic is added to the IC. Major advantages compared to MISR (Multiple-Input Signature Register) based schemes are that our scheme (1) allows abort-on-fail testing at clock-cycle granularity, (2) does not impact diagnostic capabilities, and (3) needs no special care for the handling of unknowns (X).

Detaljer

Författare
Externa organisationer
  • External Organization - Unknown
Forskningsområden

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Elektroteknik och elektronik

Nyckelord

Originalspråkengelska
Titel på värdpublikation[Host publication title missing]
FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor726-731
ISBN (tryckt)1-4244-0629-3
StatusPublished - 2007
PublikationskategoriForskning
Peer review utfördJa
Externt publiceradJa
EvenemangAsia and South Pacific Design Automation Conference ASP-DAC '07 - Yokohama, Japan
Varaktighet: 2007 jan 232007 jan 26

Konferens

KonferensAsia and South Pacific Design Automation Conference ASP-DAC '07
LandJapan
OrtYokohama
Period2007/01/232007/01/26