An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

Abstract

An on-chip, low power, and area efficient charge-pump (CP) that generates a multiple of the supply voltage (VDD) in a single clock cycle is presented. The proposed CP utilizes parallel cross-connected CP units, which are implemented using MIM (metal-insulator-metal) capacitors. In the target application, i.e., a sub-threshold SRAM, the capacitors are accommodated on top of the memory banks to remove their area cost, which dominates in a CP realization. In this work, 66 instances of the proposed CP are fully integrated on-chip to assist read and write operations. The design is manufactured in a commercial 28nm FD-SOI technology and different design parameters were verified by measurements. The results verify an increased system-wise performance and power efficiency at a low area overhead of 3.7%. A performance of 37.5MHz for a boost ratio of 2×, and an average energy dissipation of 41 fJ per operation, was observed at 0.36V.

Detaljer

Författare
Enheter & grupper
Externa organisationer
  • Lund University
Forskningsområden

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Annan elektroteknik och elektronik
Originalspråkengelska
Titel på värdpublikation 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)
FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor229-232
ISBN (elektroniskt)978-150903700-1
StatusPublished - 2017
PublikationskategoriForskning
Peer review utfördJa
EvenemangIEEE Asian Solid-State Circuits Conference (A-SSCC ). 2016 - Toyama International Conference Center, Toyama, Japan
Varaktighet: 2016 nov 72016 nov 9

Konferens

KonferensIEEE Asian Solid-State Circuits Conference (A-SSCC ). 2016
LandJapan
OrtToyama
Period2016/11/072016/11/09