An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI

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Standard

An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI. / Mohammadi, Babak; Andersson, Oskar; Luo, Xiao; Nouripayam, Masoud; Rodrigues, Joachim.

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE - Institute of Electrical and Electronics Engineers Inc., 2017. s. 229-232.

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

Harvard

Mohammadi, B, Andersson, O, Luo, X, Nouripayam, M & Rodrigues, J 2017, An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI. i 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE - Institute of Electrical and Electronics Engineers Inc., s. 229-232, IEEE Asian Solid-State Circuits Conference (A-SSCC ). 2016, Toyama, Japan, 2016/11/07. https://doi.org/10.1109/ASSCC.2016.7844177

APA

Mohammadi, B., Andersson, O., Luo, X., Nouripayam, M., & Rodrigues, J. (2017). An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI. I 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC) (s. 229-232). IEEE - Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2016.7844177

CBE

Mohammadi B, Andersson O, Luo X, Nouripayam M, Rodrigues J. 2017. An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI. I 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE - Institute of Electrical and Electronics Engineers Inc. s. 229-232. https://doi.org/10.1109/ASSCC.2016.7844177

MLA

Mohammadi, Babak et al. "An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI". 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE - Institute of Electrical and Electronics Engineers Inc. 2017, 229-232. https://doi.org/10.1109/ASSCC.2016.7844177

Vancouver

Mohammadi B, Andersson O, Luo X, Nouripayam M, Rodrigues J. An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI. I 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE - Institute of Electrical and Electronics Engineers Inc. 2017. s. 229-232 https://doi.org/10.1109/ASSCC.2016.7844177

Author

Mohammadi, Babak ; Andersson, Oskar ; Luo, Xiao ; Nouripayam, Masoud ; Rodrigues, Joachim. / An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI. 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE - Institute of Electrical and Electronics Engineers Inc., 2017. s. 229-232

RIS

TY - GEN

T1 - An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI

AU - Mohammadi, Babak

AU - Andersson, Oskar

AU - Luo, Xiao

AU - Nouripayam, Masoud

AU - Rodrigues, Joachim

PY - 2017

Y1 - 2017

N2 - An on-chip, low power, and area efficient charge-pump (CP) that generates a multiple of the supply voltage (VDD) in a single clock cycle is presented. The proposed CP utilizes parallel cross-connected CP units, which are implemented using MIM (metal-insulator-metal) capacitors. In the target application, i.e., a sub-threshold SRAM, the capacitors are accommodated on top of the memory banks to remove their area cost, which dominates in a CP realization. In this work, 66 instances of the proposed CP are fully integrated on-chip to assist read and write operations. The design is manufactured in a commercial 28nm FD-SOI technology and different design parameters were verified by measurements. The results verify an increased system-wise performance and power efficiency at a low area overhead of 3.7%. A performance of 37.5MHz for a boost ratio of 2×, and an average energy dissipation of 41 fJ per operation, was observed at 0.36V.

AB - An on-chip, low power, and area efficient charge-pump (CP) that generates a multiple of the supply voltage (VDD) in a single clock cycle is presented. The proposed CP utilizes parallel cross-connected CP units, which are implemented using MIM (metal-insulator-metal) capacitors. In the target application, i.e., a sub-threshold SRAM, the capacitors are accommodated on top of the memory banks to remove their area cost, which dominates in a CP realization. In this work, 66 instances of the proposed CP are fully integrated on-chip to assist read and write operations. The design is manufactured in a commercial 28nm FD-SOI technology and different design parameters were verified by measurements. The results verify an increased system-wise performance and power efficiency at a low area overhead of 3.7%. A performance of 37.5MHz for a boost ratio of 2×, and an average energy dissipation of 41 fJ per operation, was observed at 0.36V.

U2 - 10.1109/ASSCC.2016.7844177

DO - 10.1109/ASSCC.2016.7844177

M3 - Paper in conference proceeding

SP - 229

EP - 232

BT - 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE Asian Solid-State Circuits Conference (A-SSCC ). 2016

Y2 - 7 November 2016 through 9 November 2016

ER -