An ASIC Implementation for V-BLAST Detection in 0.35um CMOS

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

Abstract

The V-BLAST system has been shown to be capable of exploiting the capacity advantage of multiple antenna systems. The square root algorithm for V-BLAST detection is attractive to hardware implementations due to low computational complexity and numerical stability. A low complexity VLSI architecture of the square root algorithm is presented in this paper. The proposed architecture is scalable for various configurations, and implemented in AMIS 0.35 /spl mu/m CMOS technology for a 4/spl times/4 QPSK V-BLAST system. When the received symbol packet length is larger than or equal to 100 bytes, the implemented chip can achieve a maximally possible detection throughput of 128/spl sim/160 Mb/s with a maximal clock frequency of 80 MHz.

Detaljer

Författare
  • Zhan Guo
  • Peter Nilsson
Enheter & grupper
Forskningsområden

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Elektroteknik och elektronik
Originalspråkengelska
Titel på värdpublikationProceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004.
Sidor95-98
StatusPublished - 2004
PublikationskategoriForskning
Peer review utfördJa
EvenemangFourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT - Rome, Italien
Varaktighet: 2004 dec 182004 dec 21

Konferens

KonferensFourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT
LandItalien
OrtRome
Period2004/12/182004/12/21