An ASIC Implementation for V-BLAST Detection in 0.35um CMOS

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Bibtex

@inproceedings{9982a949b8334493b7cdf63c587a47f9,
title = "An ASIC Implementation for V-BLAST Detection in 0.35um CMOS",
abstract = "The V-BLAST system has been shown to be capable of exploiting the capacity advantage of multiple antenna systems. The square root algorithm for V-BLAST detection is attractive to hardware implementations due to low computational complexity and numerical stability. A low complexity VLSI architecture of the square root algorithm is presented in this paper. The proposed architecture is scalable for various configurations, and implemented in AMIS 0.35 /spl mu/m CMOS technology for a 4/spl times/4 QPSK V-BLAST system. When the received symbol packet length is larger than or equal to 100 bytes, the implemented chip can achieve a maximally possible detection throughput of 128/spl sim/160 Mb/s with a maximal clock frequency of 80 MHz.",
author = "Zhan Guo and Peter Nilsson",
year = "2004",
doi = "10.1109/ISSPIT.2004.1433696",
language = "English",
isbn = "0-7803-8689-2",
pages = "95--98",
booktitle = "Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004.",
note = "Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT ; Conference date: 18-12-2004 Through 21-12-2004",

}