Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si

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Abstract

We use a self-aligned, gate-last process providing n-type (InAs) and p-type (GaSb) MOSFET co-integration with a common gate-stack and demonstrate balanced drive current capability at about 100 μA/μm . By utilizing HSQ-spacers, control of gate-alignment allows to fabricate both n- and p-type devices based on the same type of vertical heterostructure InAs/GaSb nanowire with short gate-lengths down to 60 nm. Refined digital etch techniques, compatible with both sensitive antimonide structures and InAs, enable down to 16 nm diameter GaSb channel regions and 10 nm InAs channels. Balanced performance is showcased for both n- and p-type MOSFETs with Ion=156 μA/μm , at Ioff=100 nA/μm , and 98μA/μm , at |VDS|=0.5 , respectively.

Detaljer

Författare
Enheter & grupper
Forskningsområden

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Annan elektroteknik och elektronik

Nyckelord

Originalspråkengelska
Titel på värdpublikation2018 IEEE International Electron Devices Meeting (IEDM)
FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor39.3.1-39.3.4
ISBN (elektroniskt)978-1-7281-1987-8
ISBN (tryckt)978-1-7281-1988-5
StatusPublished - 2019 jan 17
PublikationskategoriForskning
Peer review utfördJa
Evenemang64th IEEE International Electron Devices Meeting - San Francisco, USA
Varaktighet: 2018 dec 12018 dec 5
Konferensnummer: 64

Konferens

Konferens64th IEEE International Electron Devices Meeting
Förkortad titelIEDM 2018
LandUSA
OrtSan Francisco
Period2018/12/012018/12/05

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