Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si

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Bibtex

@inproceedings{d37499f795c9415693e7fe2cf3dc18b4,
title = "Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si",
abstract = "We use a self-aligned, gate-last process providing n-type (InAs) and p-type (GaSb) MOSFET co-integration with a common gate-stack and demonstrate balanced drive current capability at about 100 μA/μm . By utilizing HSQ-spacers, control of gate-alignment allows to fabricate both n- and p-type devices based on the same type of vertical heterostructure InAs/GaSb nanowire with short gate-lengths down to 60 nm. Refined digital etch techniques, compatible with both sensitive antimonide structures and InAs, enable down to 16 nm diameter GaSb channel regions and 10 nm InAs channels. Balanced performance is showcased for both n- and p-type MOSFETs with Ion=156 μA/μm , at Ioff=100 nA/μm , and 98μA/μm , at |VDS|=0.5 , respectively.",
keywords = "Logic gates, Nanoscale devices, MOSFET, Performance evaluation, Ions, Silicon, Metals",
author = "Adam J{\"o}nsson and Johannes Svensson and Lars-Erik Wernersson",
year = "2019",
month = jan,
day = "17",
doi = "10.1109/IEDM.2018.8614685",
language = "English",
isbn = "978-1-7281-1988-5",
pages = "39.3.1--39.3.4",
booktitle = "2018 IEEE International Electron Devices Meeting (IEDM)",
publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",
note = "null ; Conference date: 01-12-2018 Through 05-12-2018",

}