Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

Standard

Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si. / Jönsson, Adam; Svensson, Johannes; Wernersson, Lars-Erik.

2018 IEEE International Electron Devices Meeting (IEDM). IEEE - Institute of Electrical and Electronics Engineers Inc., 2019. s. 39.3.1-39.3.4.

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

Harvard

Jönsson, A, Svensson, J & Wernersson, L-E 2019, Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si. i 2018 IEEE International Electron Devices Meeting (IEDM). IEEE - Institute of Electrical and Electronics Engineers Inc., s. 39.3.1-39.3.4, 64th IEEE International Electron Devices Meeting, San Francisco, USA, 2018/12/01. https://doi.org/10.1109/IEDM.2018.8614685

APA

Jönsson, A., Svensson, J., & Wernersson, L-E. (2019). Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si. I 2018 IEEE International Electron Devices Meeting (IEDM) (s. 39.3.1-39.3.4). IEEE - Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2018.8614685

CBE

Jönsson A, Svensson J, Wernersson L-E. 2019. Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si. I 2018 IEEE International Electron Devices Meeting (IEDM). IEEE - Institute of Electrical and Electronics Engineers Inc. s. 39.3.1-39.3.4. https://doi.org/10.1109/IEDM.2018.8614685

MLA

Jönsson, Adam, Johannes Svensson, och Lars-Erik Wernersson "Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si". 2018 IEEE International Electron Devices Meeting (IEDM). IEEE - Institute of Electrical and Electronics Engineers Inc. 2019, 39.3.1-39.3.4. https://doi.org/10.1109/IEDM.2018.8614685

Vancouver

Jönsson A, Svensson J, Wernersson L-E. Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si. I 2018 IEEE International Electron Devices Meeting (IEDM). IEEE - Institute of Electrical and Electronics Engineers Inc. 2019. s. 39.3.1-39.3.4 https://doi.org/10.1109/IEDM.2018.8614685

Author

Jönsson, Adam ; Svensson, Johannes ; Wernersson, Lars-Erik. / Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si. 2018 IEEE International Electron Devices Meeting (IEDM). IEEE - Institute of Electrical and Electronics Engineers Inc., 2019. s. 39.3.1-39.3.4

RIS

TY - GEN

T1 - Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si

AU - Jönsson, Adam

AU - Svensson, Johannes

AU - Wernersson, Lars-Erik

N1 - Conference code: 64

PY - 2019/1/17

Y1 - 2019/1/17

N2 - We use a self-aligned, gate-last process providing n-type (InAs) and p-type (GaSb) MOSFET co-integration with a common gate-stack and demonstrate balanced drive current capability at about 100 μA/μm . By utilizing HSQ-spacers, control of gate-alignment allows to fabricate both n- and p-type devices based on the same type of vertical heterostructure InAs/GaSb nanowire with short gate-lengths down to 60 nm. Refined digital etch techniques, compatible with both sensitive antimonide structures and InAs, enable down to 16 nm diameter GaSb channel regions and 10 nm InAs channels. Balanced performance is showcased for both n- and p-type MOSFETs with Ion=156 μA/μm , at Ioff=100 nA/μm , and 98μA/μm , at |VDS|=0.5 , respectively.

AB - We use a self-aligned, gate-last process providing n-type (InAs) and p-type (GaSb) MOSFET co-integration with a common gate-stack and demonstrate balanced drive current capability at about 100 μA/μm . By utilizing HSQ-spacers, control of gate-alignment allows to fabricate both n- and p-type devices based on the same type of vertical heterostructure InAs/GaSb nanowire with short gate-lengths down to 60 nm. Refined digital etch techniques, compatible with both sensitive antimonide structures and InAs, enable down to 16 nm diameter GaSb channel regions and 10 nm InAs channels. Balanced performance is showcased for both n- and p-type MOSFETs with Ion=156 μA/μm , at Ioff=100 nA/μm , and 98μA/μm , at |VDS|=0.5 , respectively.

KW - Logic gates

KW - Nanoscale devices

KW - MOSFET

KW - Performance evaluation

KW - Ions

KW - Silicon

KW - Metals

U2 - 10.1109/IEDM.2018.8614685

DO - 10.1109/IEDM.2018.8614685

M3 - Paper in conference proceeding

SN - 978-1-7281-1988-5

SP - 39.3.1-39.3.4

BT - 2018 IEEE International Electron Devices Meeting (IEDM)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

Y2 - 1 December 2018 through 5 December 2018

ER -