Capacitance Measurements in Vertical III-V Nanowire TFETs

Forskningsoutput: TidskriftsbidragLetter

Abstract

By measuring scattering parameters over a wide range of bias points, we study the intrinsic gate capacitance as well as the charge partitioning of vertical nanowire tunnel field-effect transistors (TFETs). The gate-to-drain capacitance Cgd is found to largely dominate the on-state of TFETs, whereas the gate-to-source capacitance Cgs is sufficiently small to be completely dominated by parasitic components. This indicates that the tunnel junction on the source side almost completely decouples the channel charge from the small-signal variation in the source, while the absence of a tunnel junction on the drain side allows the channel charge to follow the drain small-signal variation much more directly.

Detaljer

Författare
Enheter & grupper
Forskningsområden

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Annan elektroteknik och elektronik

Nyckelord

Originalspråkengelska
Sidor (från-till)943-946
Antal sidor4
TidskriftIEEE Electron Device Letters
Volym39
Utgåva nummer7
StatusPublished - 2018 maj 4
PublikationskategoriForskning
Peer review utfördJa

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