Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

Abstract

In this paper, we introduce a constraint programming-based approach for optimization of routing and reconfiguration overhead for a class of reconfigurable processor array architectures called weakly programmable. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for optimal routing of data between processors as well as for minimization of the routing area and the reconfiguration overhead when switching between the execution of these algorithms. In fact, applying the switching can be accomplished in just a few clock cycles. Our experiments confirm that our method can minimize routing overhead and reduce reconfiguration time significantly.

Detaljer

Författare
Enheter & grupper
Externa organisationer
  • University of Rennes I
  • EPI Symbiose
  • Friedrich-Alexander University Erlangen-Nürnberg
Forskningsområden

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Datavetenskap (datalogi)
Originalspråkengelska
Titel på värdpublikation11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.
FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor345-352
Antal sidor8
ISBN (tryckt)978-0-7695-3277-6
StatusPublished - 2008
PublikationskategoriForskning
Peer review utfördJa
Evenemang11th Euromicro conference on Digital System Design (DSD) - Parma, Italien
Varaktighet: 2008 sep 32008 sep 5

Konferens

Konferens11th Euromicro conference on Digital System Design (DSD)
LandItalien
OrtParma
Period2008/09/032008/09/05