Energy-minimum sub-threshold self-timed circuits using current sensing completion detection

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Bibtex

@article{37c5f69b9b33404bb18fedb7746465dd,
title = "Energy-minimum sub-threshold self-timed circuits using current sensing completion detection",
abstract = "This study addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain and a generic implementation template using bundled-data circuitry and current sensing completion detection (CSCD). Furthermore, a fully decoupled latch controller was developed, which integrates with the current-sensing circuitry. Different configurations that utilise the proposed latch controller are highlighted. A contemporary synchronous electronic design automation tools-based design flow, which transforms a synchronous design into a corresponding self-timed circuit, is outlined. Different use cases of the CSCD system are examined. The design flow and the current-sensing technique are validated by the implementation of a self-timed version of a wavelet-based event detector for cardiac pacemaker applications in a standard 65 nm CMOS process. The chip was fabricated and verified to operate down to 250 mV. Spice simulations indicate a gain of 52.58% in throughput because of asynchronous operation. By trading the throughput improvement, energy dissipation is reduced by 16.8% at the energy-minimum supply voltage.",
keywords = "ASYNCHRONOUS CIRCUITS, CMOS INTEGRATED CIRCUITS, CMOS DIGITAL INTEGRATED CIRCUITS, VLSI",
author = "OmerCan Akgun and Joachim Rodrigues and Jens Spars{\o}",
year = "2011",
doi = "10.1049/iet-cdt.2010.0118",
language = "English",
volume = "5",
pages = "342--353",
journal = "IET Computers and Digital Techniques",
issn = "1751-8601",
publisher = "Institution of Engineering and Technology",
number = "4",
note = "16th IEEE International Symposium on Asynchronous Circuits and Systems ; Conference date: 03-05-2010 Through 06-05-2010",

}