Energy-minimum sub-threshold self-timed circuits using current sensing completion detection

TY - JOUR

T1 - Energy-minimum sub-threshold self-timed circuits using current sensing completion detection

AU - Akgun, OmerCan

AU - Rodrigues, Joachim

AU - Sparsø, Jens

PY - 2011

Y1 - 2011

N2 - This study addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain and a generic implementation template using bundled-data circuitry and current sensing completion detection (CSCD). Furthermore, a fully decoupled latch controller was developed, which integrates with the current-sensing circuitry. Different configurations that utilise the proposed latch controller are highlighted. A contemporary synchronous electronic design automation tools-based design flow, which transforms a synchronous design into a corresponding self-timed circuit, is outlined. Different use cases of the CSCD system are examined. The design flow and the current-sensing technique are validated by the implementation of a self-timed version of a wavelet-based event detector for cardiac pacemaker applications in a standard 65 nm CMOS process. The chip was fabricated and verified to operate down to 250 mV. Spice simulations indicate a gain of 52.58% in throughput because of asynchronous operation. By trading the throughput improvement, energy dissipation is reduced by 16.8% at the energy-minimum supply voltage.

AB - This study addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain and a generic implementation template using bundled-data circuitry and current sensing completion detection (CSCD). Furthermore, a fully decoupled latch controller was developed, which integrates with the current-sensing circuitry. Different configurations that utilise the proposed latch controller are highlighted. A contemporary synchronous electronic design automation tools-based design flow, which transforms a synchronous design into a corresponding self-timed circuit, is outlined. Different use cases of the CSCD system are examined. The design flow and the current-sensing technique are validated by the implementation of a self-timed version of a wavelet-based event detector for cardiac pacemaker applications in a standard 65 nm CMOS process. The chip was fabricated and verified to operate down to 250 mV. Spice simulations indicate a gain of 52.58% in throughput because of asynchronous operation. By trading the throughput improvement, energy dissipation is reduced by 16.8% at the energy-minimum supply voltage.

KW - ASYNCHRONOUS CIRCUITS

KW - CMOS INTEGRATED CIRCUITS

KW - CMOS DIGITAL INTEGRATED CIRCUITS

KW - VLSI

U2 - 10.1049/iet-cdt.2010.0118

DO - 10.1049/iet-cdt.2010.0118

M3 - Article

VL - 5

SP - 342

EP - 353

JO - IET Computers and Digital Techniques

JF - IET Computers and Digital Techniques

SN - 1751-8601

IS - 4

T2 - 16th IEEE International Symposium on Asynchronous Circuits and Systems

Y2 - 3 May 2010 through 6 May 2010

ER -