Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions

Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift


In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (Dit) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in Dit as compared to planar references. It is also found that introducing tetraethyltin (TESn) doping during nanowire growth severely degrades the Dit profile. By adopting a high temperature, low V/III ratio tailored growth scheme, the influence of doping is minimized. Finally, characterization using a unique frequency behavior of the nanowire capacitance-voltage (C-V) characteristics reveals a change of the dopant incorporation mechanism as the growth condition is changed.


Enheter & grupper

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Nanoteknik


Sidor (från-till)2418-2425
Antal sidor8
TidskriftNano Letters
StatusPublished - 2016 apr 13
Peer review utfördJa

Relaterad forskningsoutput

Sofie Yngman, 2019 sep, Lund: Lund University (Media-Tryck). 215 s.

Forskningsoutput: AvhandlingDoktorsavhandling (sammanläggning)

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