Low-Frequency Noise in Nanowire and Planar III-V MOSFETs

Forskningsoutput: TidskriftsbidragArtikel i vetenskaplig tidskrift

Abstract

Nanowire geometries are leading contenders for future low-power transistor design. In this study, low-frequency noise is measured and evaluated in highly scaled III-V nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) and in planar III-V MOSFETs to investigate to what extent the device geometry affects the noise performance. Number fluctuations are identified as the dominant noise mechanism in both architectures. In order to perform a thorough comparison of the two architectures, a discussion of the underlying noise model is included. We find that the noise performance of the MOSFETs in a nanowire architecture is at least comparable to the planar devices. The input-referred voltage noise in the nanowire devices is superior by at least a factor of four.

Detaljer

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Enheter & grupper
Forskningsområden

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Nanoteknik

Nyckelord

Originalspråkengelska
Artikelnummer110986
TidskriftMicroelectronic Engineering
StatusPublished - 2019 maj 18
PublikationskategoriForskning
Peer review utfördJa

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Relaterad forskningsoutput

Markus Hellenbrand, 2020 maj, Lund: Department of Electrical and Information Technology, Lund University. 156 s.

Forskningsoutput: AvhandlingDoktorsavhandling (sammanläggning)

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