Realization of a floating-point A/D converter

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

Abstract

A floating-point analog-to-digital converter (FP-ADC) with a linear architecture has been implemented using an amplifier network in front of a pipeline ADC. The amplifier network has outputs with binary weighted gains, each sampled separately. The signal with the proper gain is then converted in the ADC. This structure allows instant floating point exponent determination. The mismatches in the amplifier network has been analyzed and successfully reduced. A prototype FP-ADC is currently being manufactured in a 0.35 μm double-poly CMOS process. Post-layout simulations show an operating frequency in excess of 30 MS/s with 74 dB dynamic range and 8 bit resolution.

Detaljer

Författare
  • Johan Piper
  • Jiren Yuan
Enheter & grupper
Forskningsområden

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Elektroteknik och elektronik
Originalspråkengelska
Titel på värdpublikationProceedings of 2001 IEEE International Symposium on Circuits and Systems
Sidor404-407
Volym1
StatusPublished - 2001
PublikationskategoriForskning
Peer review utfördJa
EvenemangIEEE International Symposium on Circuits and Systems, ISCAS, 2001 - Sydney, NSW, Australien
Varaktighet: 2001 maj 62001 maj 9

Publikationsserier

Namn
Volym1

Konferens

KonferensIEEE International Symposium on Circuits and Systems, ISCAS, 2001
Land/TerritoriumAustralien
OrtSydney, NSW
Period2001/05/062001/05/09