ZrO₂ and HfO₂ dielectrics on (001) n-InAs with atomic-layer-deposited in situ surface treatment

TY - JOUR

T1 - ZrO2 and HfO2 dielectrics on (001) n-InAs with atomic-layer-deposited in situ surface treatment

AU - Shiri Babadi, Aein

AU - Lind, Erik

AU - Wernersson, Lars Erik

PY - 2016/3/28

Y1 - 2016/3/28

N2 - The electrical properties of ZrO2 and HfO2 gate dielectrics on n-InAs were evaluated. Particularly, an in situ surface treatment method including cyclic nitrogen plasma and trimethylaluminum pulses was used to improve the quality of the high-κ oxides. The quality of the InAs-oxide interface was evaluated with a full equivalent circuit model developed for narrow band gap metal-oxide-semiconductor (MOS) capacitors. Capacitance-voltage (C-V) measurements exhibit a total trap density profile with a minimum of 1 × 1012 cm-2 eV-1 and 4 × 1012 cm-2 eV-1 for ZrO2 and HfO2, respectively, both of which are comparable to the best values reported for high-κ/III-V devices. Our simulations showed that the measured capacitance is to a large extent affected by the border trap response suggesting a very low density of interface traps. Charge trapping in MOS structures was also investigated using the hysteresis in the C-V measurements. The experimental results demonstrated that the magnitude of the hysteresis increases with increase in accumulation voltage, indicating an increase in the charge trapping response.

AB - The electrical properties of ZrO2 and HfO2 gate dielectrics on n-InAs were evaluated. Particularly, an in situ surface treatment method including cyclic nitrogen plasma and trimethylaluminum pulses was used to improve the quality of the high-κ oxides. The quality of the InAs-oxide interface was evaluated with a full equivalent circuit model developed for narrow band gap metal-oxide-semiconductor (MOS) capacitors. Capacitance-voltage (C-V) measurements exhibit a total trap density profile with a minimum of 1 × 1012 cm-2 eV-1 and 4 × 1012 cm-2 eV-1 for ZrO2 and HfO2, respectively, both of which are comparable to the best values reported for high-κ/III-V devices. Our simulations showed that the measured capacitance is to a large extent affected by the border trap response suggesting a very low density of interface traps. Charge trapping in MOS structures was also investigated using the hysteresis in the C-V measurements. The experimental results demonstrated that the magnitude of the hysteresis increases with increase in accumulation voltage, indicating an increase in the charge trapping response.

U2 - 10.1063/1.4945430

DO - 10.1063/1.4945430

M3 - Article

AN - SCOPUS:84964329817

VL - 108

JO - Applied Physics Letters

JF - Applied Physics Letters

SN - 0003-6951

IS - 13

M1 - 132904

ER -