Erik Larsson received his M.Sc., Tech. Lic, Ph.D, and Docent from Linköping University in 1994, 1998, 2000, 2006,  respectively. He did his Post Doc at the Computer Design and Test Laboratory at Nara Institute of Science and Technology (NAIST), Japan (October 2001-December 2002) , and was through Swedish Foundation for Strategic Research (SSF) (Strategic mobility) at NXP Semiconductors, Eindhoven, The Netherlands (October 2008-May 2010). From 2002 until 2012 he was with Linköping University as an Assistant Professor (2002-2005) and as Associate Professor (2006-2012). He joined Lund University as Associate Professor in 2012. From 2018 he is Professor in Computer Architecture. 

His current research interests include test planning for manufacturing test, test during operation (in-situ), scan-chain diagnosis, silicon debug and validation, IJTAG/SJTAG, stacked 3D chip test, fault-tolerance for MPSoCs (Multi-Processor System-on-Chip), and property checking in distributed systems (MPSOcS with Network-on-Chip (NoC)). He authored the book Introduction to Advanced System-on-Chip Test Design and Optimization (Springer 2005). Erik Larsson is a Senior member of IEEE.

He has received a number of best paper awards: 

• "Integrated Test Scheduling, Test Parallelization and TAM Design" received the best paper award at IEEE Asian Test Symposium (ATS), 2002
• "Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment" received the Institution of Engineering and Technology (IET) Premium Award, 2009
• "A Self-Reconfiguring IEEE 1687 Network for Fault Monitoring" received the best paper award at the IEEE European Test Symposium (ETS), 2016
• “Test Flow Selection for Stacked Integrated Circuits” received the 2019 JETTA-TTTC Best Paper Award 

He supervised the following awardes theses: 

• Best Bachelor thesis at Linköping University supported by Föreningen Svenskt Näringsliv, 2002
• Best thesis at the Department of Computer and Information Science, 2004 and 2005
• Best Master thesis in Engineering in Sweden ( "Lilla Polhemspriset" 2008)

Some other recognitions:

•  "An Integrated System-on-Chip Test Framework" has been selected to be included in Design, Automation, and Test in Europe, The Most Influential Papers of 10 Years DATE, 2008
• "Integrated Test Scheduling, Test Parallelization and TAM Design" has been selected to be included in the Asian Test Symposium 20th Anniversary Compendium of Papers (2011)
• "Design, Verification, and Application of IEEE 1687" has been selected to be included in the Asian Test Symposium 30th Anniversary Compendium of Papers (2021)