Erik Larsson is Professor at the Department of Electrical and Information Technology at Lund University (LU).

He received his M.Sc., Tech. Lic, Ph.D, and Docent from Linköping University in 1994, 1998, 2000, 2006,  respectively. He did his Post Doc (Oct. 2001-Dec. 2002) at the Computer Design and Test Laboratory at Nara Institute of Science and Technology (NAIST), Japan, and was through Swedish Foundation for Strategic Research (SSF) (Strategic mobility) at NXP Semiconductors, Eindhoven, The Netherlands (Oct. 2008-May 2010). From 2002 until 2012 he was with Linköping University as an Assistant Professor (2002-2005) and as Associate Professor (2006-2012). He joined Lund University as Associate Professor in 2012. From 2018 he is Professor in Computer Architecture. 

His current research interests include test planning for manufacturing test, test during operation (in-situ), scan-chain diagnosis, silicon debug and validation, IJTAG/SJTAG, stacked 3D chip test, fault-tolerance for MPSoCs (Multi-Processor System-on-Chip), and property checking in distributed systems (MPSOcS with Network-on-Chip (NoC)). He has more than 130 publications in these areas.

He has received a number of best paper awards: 

• "Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment" received the Institution of Engineering and Technology (IET) Premium Award (photo), 2009,
• "Integrated Test Scheduling, Test Parallelization and TAM Design" received the best paper award at IEEE Asian Test Symposium (ATS), 2002, (photo1, photo2)
• "A Self-Reconfiguring IEEE 1687 Network for Fault Monitoring" received the best paper award at the IEEE European Test Symposium (ETS), 2016. 
• “Test Flow Selection for Stacked Integrated Circuits” received the 2019 JETTA-TTTC Best Paper Award 

His paper "An Integrated System-on-Chip Test Framework" has been selected to be included in Design, Automation, and Test in Europe, The Most Influential Papers of 10 Years DATE, 2008, and the paper "Integrated Test Scheduling, Test Parallelization and TAM Design" was included in the ATS 20th Anniversary Compendium of Papers (2011). 

He authored the book Introduction to Advanced System-on-Chip Test Design and Optimization (Springer 2005). And he supervised theses that won prize as best Master thesis in Engineering in Sweden ( "Lilla Polhemspriset" 2008), best thesis 2004 and 2005 at the Department of Computer and Information Science, and best Bachelor thesis at Linköping University supported by Föreningen Svenskt Näringsliv, 2002. Erik Larsson is in a number of committees, has/had several research projects and is Senior member of IEEE.