A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL

Ying Wu; Ping Lu; Robert Bogdan Staszewski

doi:10.1109/RFIC.2015.7337713

A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL

Ying Wu, Ping Lu, Robert Bogdan Staszewski

Institutionen för elektro- och informationsteknik

Delft University of Technology

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

Sammanfattning

A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.

Originalspråk	engelska
Titel på värdpublikation	2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Förlag	IEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor	95-98
ISBN (elektroniskt)	978-1-4799-7642-3
DOI	https://doi.org/10.1109/RFIC.2015.7337713
Status	Published - 2015
Evenemang	IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015 - Phoenix, Arizona, USA Varaktighet: 2015 maj 17 → 2015 maj 19

Konferens

Konferens	IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015
Land/Territorium	USA
Ort	Phoenix, Arizona
Period	2015/05/17 → 2015/05/19

Ämnesklassifikation (UKÄ)

Elektroteknik och elektronik

Tillgång till dokument

10.1109/RFIC.2015.7337713

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@inproceedings{1555f3506496471f98f9ebab25f1bc9f,

title = "A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL",

abstract = "A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.",

author = "Ying Wu and Ping Lu and Staszewski, {Robert Bogdan}",

year = "2015",

doi = "10.1109/RFIC.2015.7337713",

language = "English",

pages = "95--98",

booktitle = "2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015 ; Conference date: 17-05-2015 Through 19-05-2015",

}

Wu, Y, Lu, P & Staszewski, RB 2015, A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL. i 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE - Institute of Electrical and Electronics Engineers Inc., s. 95-98, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, Phoenix, Arizona, USA, 2015/05/17. https://doi.org/10.1109/RFIC.2015.7337713

A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL. / Wu, Ying; Lu, Ping; Staszewski, Robert Bogdan.
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE - Institute of Electrical and Electronics Engineers Inc., 2015. s. 95-98.

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

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AB - A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.

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DO - 10.1109/RFIC.2015.7337713

M3 - Paper in conference proceeding

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BT - 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015

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ER -

A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL

Sammanfattning

Konferens

Ämnesklassifikation (UKÄ)

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